Application
3D NAND
HV CMOS with better performance leveraging MST Power Devices know-how.
3D NAND · The demand
Agentic AI needs memory for context
AI agents work through long tasks and keep their working context — conversation history, retrieved documents, intermediate results — instead of starting over each time. That context outgrows DRAM and moves to fast, high-capacity SSDs next to the GPUs.
Every one of those SSDs is built on 3D NAND, and NAND makers raise density by stacking more layers: 400 and beyond.
The problem
More layers need more high-voltage word-line drivers
Each word line in the stack is driven through a high-voltage (≈20 V) pass transistor in the CMOS under the array. About a million of them per chip, and the count rises with every added layer.
Logic transistors shrink with each node; these do not. Punch-through and snapback at 20 V fix their gate length and pitch, so their area grows with every node and dominates the CMOS chip.
Thin oxide · 2 nm
Area shrinks with every node
Page-buffer latches and logic; I/O, control and ECC (10²–10³ devices, speed-driven by Ion).
Thick oxide · 42 nm
Area increases with every node
≈10⁶
Word-line pass transistors
One per block per word line, so the count grows with the number of NAND layers. Lg 1.2 µm, pitch 2.58 µm, limited by punch-through and snapback.
≈10⁵
Bit-line select
Isolates the page buffer while the array is erased.
≈10³
Pumps, level shifters, CG drivers
Sized by the programming voltage.
What MST does
Anchors the well doping so the 20 V transistor can shrink
Punch-through and snapback come from well and channel doping that spreads during the thermal budget. MST holds those dopants where the design puts them, the same diffusion blocking proven in Atomera's power devices.
With the well profile anchored, the high-voltage transistor keeps its 20 V capability at a shorter gate length and tighter pitch, and the CMOS under the array stops growing with each layer count.
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