MST Properties & Uses

What MST does inside the transistor.

Properties

Diffusion Blocking Dopant Profile Surface Roughness Gate Oxide Quality SBH Reduction

Executive summary

Five properties, one film

MST creates a thermodynamically stable environment that blocks dopants. Engineered dopant profiles form, and survive high thermal budgets.

Diffusion Blocking

Holds dopants in place through high thermal budgets, including oxidation-enhanced diffusion.

See the data

Dopant Profile Engineering

Profiles built for each application: lower resistance, abrupt interfaces, new transistor designs.

See the data

Surface Roughness Reduction

A smoother Si/SiO₂ interface: about half the surface-roughness scattering.

See the data

Gate Oxide Quality Improvement

A better silicon/gate-oxide interface for poly/SiON and HKMG transistors.

See the data

Schottky Barrier Height (SBH) Reduction

A lower Schottky barrier at the metal/silicon interface: lower contact resistance.

See the data

MSTcad™

Model MST in your own process and device flow

Atomera's TCAD library for Synopsys Sentaurus.

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MST property

Diffusion Blocking

MST traps the silicon interstitials that carry dopants, so dopants stay put through the thermal budget.

It also strongly retards oxidation-enhanced diffusion.

Same implant, same anneal

Without MST, oxidation-enhanced diffusion spreads the boron. With MST, the as-implanted peak stays and the surface stays lightly doped.

Boron profile change — no MSTBoron spreads during the anneal.

Boron profile change — with MSTThe as-implanted boron peak is kept.

Diffusion blocking for various species

SIMS depth profiles. Top: silicon control (orange) vs MST (blue), with the profile slope at the MST in nm/decade. Bottom: after epi and after gate oxidation + 1000 °C anneal.

Blocking across device types

S/D phosphorus blocking for GAA nanosheets

Ga blocking: SIMS of GaN/AlN on Si(111), reference vs MST

MST property

Dopant Profile Engineering

MST lets each application have its own dopant profile: lower resistance, abrupt interfaces, new transistor designs.

RF-SOI boron doping profile: SIMS and MSTcad™ model

4F² DRAM Vertical Access Transistor Phosphorus Doping ProfileTCAD simulation.

MST property

Surface Roughness Reduction

MST gives a smoother Si/SiO₂ interface, so electrons scatter less.

Electron surface-roughness scatteringMST: 50% less electron surface-roughness scattering.

MST property

Gate Oxide Quality Improvement

MST improves the silicon/gate-oxide interface, for both poly/SiON and HKMG transistors.

Gate dielectric improvement

Gate leakage (Jg)MST: lower gate leakage.

Gate oxide integrityMST: better gate oxide integrity.

MST property

Schottky Barrier Height (SBH) Reduction

MST lowers the barrier at the metal/silicon contact, which lowers contact resistance.

Richardson plots, MST vs controlMST: 260 mV lower Schottky barrier height.

Learn more: whitepapers & publications

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