Application

Analog & Power

Lower on-resistance at the same breakdown and reliability, from low-voltage BCD switches to LDMOS.

Applications

Leading Logic DRAM 3D NAND Analog & Power GaN-on-Si RF-SOI Whitepapers All applications

Analog & Power

LV BCD LDMOS

How MST helps

Shorter, stronger power switches

Shrinking a power switch lowers its on-resistance, until spreading dopants cost breakdown or reliability. MST holds those dopants in place, in the same BCD or discrete flow.

Device	Range	What MST does	Result
Low-voltage switch	5 V · BCD	Blocks boron in the body, slows source/drain-extension spread, enables Lg scaling	Delivers best-in-class RspSilicon
LDMOS	5–48 V · BCD	Holds a doped surface layer in the drift; blocks boron from diffusing up into the channel	8–20% lower on-resistance at the same breakdown; breaks the 1-D silicon Rsp vs. BVdss limitMSTcad™ simulation · In R&D

LV BCD · Source engineering · silicon

A shorter gate that still meets SOA

MST slows lateral dopant diffusion, so the effective channel is longer than the drawn gate: lower peak field and impact ionization. Same device doping as the silicon control, 180 nm foundry process.

−18%

specific on-resistance vs the silicon control, same device doping

Silicon

0.25 µm

gate length that meets SOA, vs 0.27 µm for the silicon control, comparable HCI margin

Silicon

+25–33 nm

effective channel length at the same drawn gate (SCM, NMOS and PMOS)

Silicon

Source engineering (concept)① core shallow LDD ② source-only halo ③ shallow p-body under the source ④ baseline drain kept.

2D doping (SCM), gate length 0.5 µmMST: effective channel +25 nm (NMOS) and +33 nm (PMOS) over the silicon control.

SOA vs gate lengthMST meets the SOA spec down to 0.25 µm; the silicon control to 0.27 µm.

Specific on-resistance vs breakdownMST: 18% lower R_SP at the same BV_DSS.

LDMOS · 5–48 V · MSTcad™ simulation

LDMOSIn R&D

MST carries the switch's source engineering into an LDMOS and holds a doped surface layer in the drift. Projected with MSTcad™ from MST silicon, it beats published BCD LDMOS at the same breakdown and breaks the 1-D silicon R_SP vs BV_DSS limit.

Silicon power-switch benchmark: R_SP vs BV_DSSMST silicon at 11 V and the MSTcad™ projection vs published 0.16–0.18 µm BCD LDMOS (ISPSD 2010–2021) and the classical Si limit (C. Hu, 1979).MST: below published BCD LDMOS across 10–50 V, and past the 1-D silicon limit above 36 V.

Below BCD

lower R_SP than leading 0.16–0.18 µm BCD platforms across 10–50 V

MSTcad™ projection

>36 V

where the projected R_SP passes the classical 1-D silicon limit

MSTcad™ projection

11 V

starting point: MST silicon; the model deck is validated on it

Silicon

Drift engineering · MSTcad™ projection

Past the classical silicon limit

MST piles up phosphorus near the drift-layer surface; source engineering lowers the body resistance for a higher on-state breakdown. Same drift and RESURF implants as the silicon control.

−8 to −20%

R_SP across 10–50 V BV_DSS

MSTcad™ projection

Beyond 1-D

the silicon R_SP vs BV_DSS limit, for BV_DSS above 36 V

MSTcad™ projection

+2–4 V

on-state breakdown, or >25% lower R_SP at the same on-state breakdown

MSTcad™ projection

Drift phosphorus (SIMS)MST: a near-surface phosphorus peak. Silicon.

R_SP vs BV_DSS−8 to −20% R_SP from 10 to 50 V. MSTcad™ projection.

R_SP vs on-state breakdown+2–4 V, or >25% lower R_SP. MSTcad™ projection.

Buried-channel LDMOS · MSTcad™ projection

A buried channel that extends the hot-carrier limit

A p⁺ poly gate and shallow n⁻ counter-doping move electrons off the interface. MST keeps the counter-doping shallow and the p-body in place, so only with MST does the buried channel keep its on-state breakdown. 16 V LDMOS: 12.5 nm oxide, 1.2 µm device, 0.68 µm gate, step oxide, field plate in the drift.

>18 V

on-state breakdown of a 16 V device (TLP), vs below 13 V for a silicon-control buried channel

MSTcad™ projection

~20%

better R_ON than a conventional surface-channel LDMOS

MSTcad™ projection

+2 V

BV_DSS vs surface channel: R_ON and on-state breakdown together only with MST

MSTcad™ projection

Surface vs buried channel (concept)p⁺ poly gate + n⁻ counter-doping.

Doping maps at optimum breakdownThe silicon control loses the p-body; MST keeps it. MSTcad™ projection.

Turn-on, off-state and on-state breakdown+20% drive, +2 V off-state breakdown, on-state breakdown >18 V with MST vs <13 V for the silicon-control buried channel. MSTcad™ projection.

Learn more: whitepapers & publications

Work with us

Partner with Atomera

Evaluate MST in your own process and devices with Atomera's engineering team.