Application

DRAM

MST for DRAM: 4F² vertical-channel cells, faster base-die transistors for HBM, and etch stops inside silicon.

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DRAM

4F² DRAM FinFET & GAA for HBM

4F² DRAM

The vertical access transistor: the problem, and the MST solution

The problem

h⁺

The gate edge creates holes

Gate-induced drain leakage (GIDL) holes charge the floating body and drain the stored bit.

Phosphorus diffuses out of the source/drain

Less doping where it is needed reduces drive current.

The MST solution

✓

Prevents hole generation

GIDL suppressed, so no floating body.

✓

Blocks phosphorus movement

The graded LDD stays in place.

✓

Simpler process

selective-epi steps eliminated

wafer-bonding module eliminated

✓

A blanket quantum-engineered MST film on the silicon substrate

GIDL: gate-induced drain leakage · LDD: lightly doped drain · S/D: source/drain

4F² DRAM · The device modeled

Put the doping in the starting wafer

Today's 4F² flows build the storage-node and bit-line doping with selective epitaxy, each on a separately bonded wafer. Atomera's SISPAD 2026 study puts the vertical doping profile in the starting substrate instead, held in place by eight MST layers in the drain and source regions.

That removes two selective-epitaxy modules and one wafer bond — if the profile survives everything that follows.

The vertical-channel transistor modeled: control vs MSTTCAD: active phosphorus along the pillar after the DRAM thermal budget. The MST pillar keeps its drain and source doping; the control's spreads out.

Typical flow

Si substrate→Etch pillars→Gate→Storage-node doping (SEG)→Wafer bond→Bit-line doping (SEG)→Wafer bond

With MST

MST substrate, doping pre-defined→Etch pillars→Gate→Wafer bond

Struck-through: steps the MST substrate removes (two selective-epitaxy modules and one wafer bond). Simplified from the paper's flow comparison.

4F² DRAM · What MST enables

Phosphorus held in place, floating-body effect suppressed

The thermal gate oxide is the worst of the DRAM thermal budget: oxidation injects silicon interstitials, and oxidation-enhanced diffusion pulls phosphorus out of the source and drain.

MST layers block that diffusion and pile the phosphorus up next to them. The lightly doped regions stay where they keep gate-induced drain leakage — the source of the holes — low, so the floating-body effect is suppressed. The source and drain keep about ten times more active phosphorus: 2.5–3× the read/write current, still under the 20 fA/µm retention limit.

Thermal budget applieddeliberately aggressive

Step	Temperature	Time
Gate oxide (RTO, 2.7 nm)	850 °C	3 min
Source/drain activation (RTA)	950 °C	5 s
Capacitor process	750 °C	2 h

MST blocks and piles up phosphorus — measuredPhosphorus SIMS: 220 keV 8.3×10¹³ cm⁻² implant, then 750 °C 1 h. In plain Si the profile flattens to the surface; MST holds it below and piles it up at the layer.

2.5–3× read/write current at the same leakageTCAD: Ioff vs Ion at Vg = 1.8 V for gate work functions 4.5–4.8 eV, control vs MST substrate. At 4.75 eV both meet the retention limit.MST: 2.5–3× the read/write current of the control, with off-current still under the retention limit.

2.5–3×

read/write current vs a plain Si substrate, at the same off-current (TCAD)

<20 fA/µm

off-current kept: the retention limit (TCAD)

10×

phosphorus retained in the source/drain after the thermal budget (TCAD)

−3 steps

two selective-epitaxy modules and one wafer bond

A. Lu, M. Raj, H. Y. Wong, I. Rumyantsev, S. Li and H. Takeuchi, "Enabling 4F² DRAM Junctionless Vertical Channel Transistors with Novel Oxygen Inserted Si Substrates – A TCAD Study," SISPAD 2026 (Atomera and San José State University).

Download the SISPAD 2026 paper

FinFET & GAA for HBM

Better base-die transistors for AI memory

AI memory bandwidth now depends on the logic base die under each HBM stack, so its transistors have to be faster.

In the nMOS source/drain epi, phosphorus diffuses into the channel and degrades performance. At 5 nm and below, an SiAs liner is added to block it. MST replaces that liner: it blocks better through the thermal cycles and brings benefits SiAs cannot.

Every bit moves through the base die

1DRAM stack: the TSVs carry the data down to the base die.
2Base die (logic): its transistors drive every bit on and off the stack.
3Si interposer: wires to the GPU and back, for every read and write.

Why the base die needs leading-edge logic

Energy

Every bit the accelerator reads or writes is driven through the base die and across the interposer, and every move costs energy.

Heat

That energy turns into heat under the DRAM stack, inside a package that has to stay within its thermal limits.

Leading-edge logic

Faster, lower-power transistors in the base die cut both. That is moving HBM base dies to leading-edge FinFET and GAA logic.

Stronger blocking

Holds phosphorus out of the channel through the thermal cycles better than SiAs.

50%+ more active dopant

More of the source/drain phosphorus is electrically active.

Sharper profile

A more abrupt junction allows tighter control of gate length (Lg).

Scales with geometry

A thinner film gives the same performance as the device shrinks.

>10%

MST enables more than 10% improvement in Idsat, which can be leveraged for energy reduction.

3D TCAD, FinFET nMOS, vs a silicon control.

Same speed, lower voltage

More current per transistor reaches the same speed at a lower supply voltage. Switching energy scales with the square of the voltage, so a small voltage cut saves proportionally more energy.

Same speed, smaller transistors

Or keep the voltage and get the same drive from smaller transistors: less capacitance to charge on every switch, and less leakage.

Less heat in the stack

Lower power in the base die means less heat under the DRAM stack, easing the package's thermal limit.

Learn more: whitepapers & publications

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