Application

Leading Logic

FinFET and gate-all-around transistors with sharper junctions, a thinner gate stack and a lower-resistance contact, and better planar CMOS, from one epitaxial film.

Applications

Leading Logic DRAM 3D NAND Analog & Power GaN-on-Si RF-SOI Whitepapers All applications

Leading Logic

FinFET & GAA Planar CMOS

FinFET & GAA

Four applications being investigated to improve drive current and lower contact resistance

At each new node a few nanometres of dopant spread decide the device. MST goes in at four places, in epitaxy steps the flow already has.

>+10%

drive current (Ion) on 2 nm GAA from a sharper source/drain junction

3D TCAD

Lower work function

on HfO₂, so a thinner work-function metal fits between sheets

Silicon

Lower contact resistivity

from a lower Schottky barrier

Silicon

1S/D liner 2Punch-through stop 3Channel & gate stack 4Contact

Source/drain liner · FinFET & GAA

1MST S/D Liner: better blocking, sharper junction, more active phosphorus

During the activation anneal, phosphorus from the SiP source/drain spreads into the channel. A thin MST liner grown first stops it. The reason only MST works is that phosphorus moves with silicon interstitials: an arsenic (SiAs) liner changes the doping but not the interstitial supply, while MST traps the interstitials. And only MST scales to next-generation GAA and CFET.

5–10×

shorter phosphorus tail than an SiAs liner, which tracks the no-liner control

Silicon

+30%

active phosphorus vs an SiAs liner at the same total phosphorus (DHEM); +8% vs no liner

Silicon

>30%

lower series resistance, estimated from measured carrier profiles

Silicon-based estimate

+10%

drive current (Idsat) at matched off-current

3D TCAD

−10–20%

DIBL

3D TCAD

The MST liner (yellow) sits between the SiP source/drain and the channel.

	SiAs liner	MST liner
Precursor	AsH₃ (toxic)	N₂O (non-toxic)
Phosphorus diffusion blocking	None — only adds distance between SiP and the channel	Yes — traps the interstitials that carry phosphorus
Sharp profile	No	Yes
SiP carrier activation	Reduced (As₄V cluster formation)	Increased (interstitial trapping)
Ion gain, 3D TCAD	+1.4%	>+10%

S/D phosphorus blocking for nanosheetPhosphorus profile, MST liner vs Si control (no liner): (100) Si, P 5 keV 1×10¹⁵ cm⁻² + 950 °C 5 s.MST suppresses phosphorus diffusion: the tail is cut 5–10× vs the Si control.

Punch-through stop · silicon

2The punch-through stop stays below the stack

A 5 nm MST film under the channel epi holds the punch-through-stop doping through epitaxy and later anneals. The channel stays undoped.

~5×

sharper edge after 1050 °C, 20 s: phosphorus decay length 4.1 vs 21.5 nm/decade

Silicon

~3×

less up-diffusion of phosphorus into undoped Si during channel epitaxy

Silicon

N and P

one film: boron is held the same way (6.6 nm MST, BF₂ punch-through stop)

Silicon

Phosphorus punch-through stop after 1050 °C, 20 sWith MST the phosphorus edge stays sharp through the anneal.

Boron punch-through stop (6.6 nm MST) after 1050 °C, 20 sOne film serves NMOS and PMOS.

Work function · silicon

3A lower work function without the extra metal

MST reduces HfO₂ intermixing and the interface dipole, so less aluminium (TiAlC) is needed in the 2–2.5 nm gap between nanosheets.

172 mV

flat-band shift, TiN/HfO₂: −0.453 V on MST vs −0.281 V on Si control

Silicon

Smaller dipole

from reduced HfO₂ intermixing at the interfacial layer

Silicon

Thinner WFM

relaxes the aluminium (TiAlC) requirement between sheets

Concept

C–V, TiN/HfO₂ stackMST shifts the flat-band voltage by 172 mV.

Contact · silicon

4A lower Schottky barrier at the contact

MST lowers the barrier and confines the heavily doped surface layer; contact resistivity falls exponentially with both.

Richardson plot after forming-gas annealUC Berkeley and Atomera, AIP Advances 2020.Schottky barrier: 330 meV with MST vs 589 meV on Si control.

−260 mV

Schottky barrier height on n⁺ Si after forming-gas anneal: 330 vs 589 meV

Silicon

−22%

specific contact resistivity

Silicon

−11%

total metal contact resistance (the interface is about half of it)

Silicon-based estimate

Silicon results are Atomera measurements and published collaborations as credited. FinFET and GAA device results are Synopsys Sentaurus 3D TCAD using measured profiles. Work-function and contact results are from test structures.

Planar CMOS