Application

Wafer Thinning Etch Stop

A thick P⁻ epi layer on a P⁺ substrate with a sharp interface, so wafer thinning and wet etch stop cleanly.

Applications

Leading Logic DRAM 3D NAND Analog & Power GaN-on-Si RF-SOI Whitepapers All applications

How MST helps

MST blocks boron diffusing up from the P⁺ substrate during thick, high-temperature epi growth. The P⁻/P⁺ interface stays sharp, giving a clean stop for wafer thinning and etch-back.

Learn more: whitepapers & publications

Boron SIMS of 2.5 µm P- epi on a P+ substrate: Si epi only vs new process with MST

Silicon data

A 9× sharper P⁻/P⁺ transition

2.5 µm P⁻ epi grown at 1050 °C on a P⁺ substrate, with and without MST first. Initial demonstration on 200 mm wafers.

0.27 → 0.03 µm

transition-layer thickness between the P⁻ epi and the P⁺ substrate

0.24 µm

closer to the design depth at 10¹⁶ cm⁻³ boron

Boron SIMS: Si epi only vs new process with MSTMST: the boron transition narrows from 0.27 to 0.03 µm, so a wet etch or thinning step stops cleanly at the interface.

applications Dopant Profile Engineering

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